Exemplary embodiments of the present invention relate to a refresh technology of a semiconductor device.
A memory cell of a semiconductor device includes a transistor, serving as a switch, and a capacitor for storing a charge, which represents data. ‘High’ (a logic value 1) and ‘low’ (a logic value 0) states of data are determined according to whether charge exists in the capacitor in the memory cell. That is, where the terminal voltage of the capacitor is high, the memory cell is said to store data of a high state, and where the terminal voltage of the capacitor is low, the memory cell is said to store data of a low state.
Since data storage is performed in such a manner that a charge is accumulated in the capacitor, no power consumption occurs principally. However, since the initial amount of charge stored in the capacitor changes due to a leakage current caused by a PN junction of a MOS transistor and the like, data may be lost. In order to prevent such a problem, it is necessary to read data from the memory cell before data is lost and perform a normal recharge operation according to the read information. The storage of data is substantially maintained only when such an operation is periodically repeated. Such a process of recharging a memory cell is referred to as a refresh operation.
In a conventional semiconductor device, if a refresh command is applied to the semiconductor device from a memory controller, all banks in the semiconductor device simultaneously perform the refresh operation. For example, all the word lines 0 to N in banks 0 to 7 are sequentially activated and data is restored.
In the conventional semiconductor device, since all the banks are simultaneously refreshed, a large amount of current is essentially consumed at one time. Furthermore, since all the banks are simultaneously refreshed, operations such as a read operation or a write operation may not be performed during the refresh operation.